finally, a compare instruction that doesn't detonate the microcontroller
Replying to @The6P4C
EIN explode immediately (never) EIN never explodes entire device immediately. in effect, this instruction can be considered a 2-byte no operation (NOP)
Show this thread
3
0
0
40
cypress made Decisions with the CY7C637(22|23|43) in building their own core, such as the fact that you must manually increment the upper byte of PC whenever you cross a 256 byte boundary

3:27 AM Β· Feb 13, 2021

8
1
0
15
a thirteen cycle instruction which does three things at once
2
2
0
16
they don't make 'em like they used to (cursed, bespoke, completely incomprehensible)
3
1
0
18
Replying to @The6P4C
MIPS: "what if we designed instruction sets in ways unfriendly to humans, but perfectly fine for machines?" Cypress: "hold my branch delay slot"
0
1
0
4
Replying to @The6P4C
tired: pipeline stall when crossing 4096 byte pages wired: manual pipeline filler when crossing 256 byte pages
0
1
0
3
Replying to @The6P4C
The custom HP processor architecture used in the HP-35 calculator (1972), and the follow-on -45, -55, -65, -70, and -80, only had an 8-bit incrementing PC. To jump to a different ROM page (one of eight) required a ROM SELECT instruction. 1/
1
0
0
3
That wasn't enough for HP-65 card-programmable, so a GROUP SELECT instruction was added. The CPU (two chips, ARC and C&T) didn't recognize either the ROM SELECT or GROUP SELECT instructions, and treated them as NO-OPs. 2/
1
0
0
1
Replying to @The6P4C @brouhaha
I sure hope that for the low low price of four clocks, you get a delay slot where it still wraps to the 1st instruction in the old page, but rest assured that this is followed by instruction 2 in the new page.
0
0
0
0
Replying to @The6P4C @brouhaha
65816 could've used an insn like this to opt out of the program bank switching scheme...
0
0
0
0
Replying to @The6P4C
Cries in -fPIC
1
0
0
2
do people use -fPIC for embedded code?
1
0
0
0